Login ㆍ Sign up
Updated: 2018.4.13 22:17
HOME > NEWS > News > News | Important News
Innovative Memory Storage
[ Issue 149 Page 3 ] Sunday, November 27, 2016, 03:36:51 Chanyoung Ryu Staff Reporter chandescartes@kaist.ac.kr

The research team headed by Professor Yang-Kyu Choi from the School of Electrical Engineering has recently developed an innovative technology that allows the combination of dynamic random access memory (DRAM) and flash memory in a single transistor. The team has worked in association with PhD students Byung-Hyun Lee from the Department of Memory Business of Samsung Electronics and Min- Ho Kang from the Department of Nano-Process of the National Nanofab Center (NNFC).

The pioneering device is the first of its kind to integrate the two types of memory in one transistor and accomplishes this feat by using vertically integrated nanowires for multifunctional unified memory.

To delve into the specifics, DRAM shows superior speed but can lose its data quickly when power is not supplied due to its volatility. On the other hand, flash memory does not lose its information from fluctuations in power but does not perform well with respect to speed. To solve this problem, the research team developed a structure that is based on a bulk silicon wafer that surrounds the wires completely. It utilizes a precise process of etching to achieve five levels of channels in its vertically integrated unified memory (VIUM), the advantages of this method including uniformness, stability, and reproducibility. Compared to the traditional one-level unified memory, the five-level VIUM shows enhanced drivability in both the DRAM and the flash memory. It also achieves a higher sensing window due to the switching endurance of the VIUM, which activates two memory modes. The device could propose a novel design in memory hierarchy based on system-on-chip architectures as it demonstrates great practicality as well as versatility and could be applied to a wide range of devices.

Professor Choi stated, “We are looking forward to an improved effectiveness in both the manufacturing process and the actual performance of memory semiconductors after our recent work. Ultimately, we look to continue the process of miniaturization of semiconductors.” Research student Lee has added, “We were able to conduct our research successfully thanks to PhD student Min-Ho Kang and his fellow researchers from the National Nanofab Center.”

The research results have been published in the monthly scientific journal Nano Letters under the title “Vertically Integrated Nanowire- Based Unified Memory”.

Chanyoung Ryu Staff Reporter Archives  
Twitter Facebook Google
ⓒ KAIST Herald 2011 (http://herald.kaist.ac.kr)
All materials on this site are protected under the Korean Copyright Law and may not be reproduced, distributed, transmitted, displayed, published without the prior consent of KAIST Herald.

Total comments(0)  
      Enter the code!   
   * Readers can write comments up to 200 words (Current 0 byte/Max 400byte)
About Us | Privacy Policy | Rights and Permissions | Article Submission | RSS | Contact Us
The KAIST Herald, Undergraduate Library, KAIST, Daejeon, Republic of Korea
Publisher: Sung-Chul Shin | Managing Editor: Jeounghoon Kim | Editor: Sejoon Huh
Copyright 2011-2018 The KAIST Herald | All rights reserved | Mail to: kaistherald@gmail.com