A KAIST research team led by Professor Kee Joo Chang and his doctoral student Sung Hyun Kim from the Department of Physics has clarified the physical properties of impurities associated with oxidized silicon nanowires. These wires are traditionally impregnated with elements such as boron and phosphorus to facilitate their current-carrying capacity, the properties of which have so far remained elusive.

Although even the latest technologies do not allow for silicon-based semiconductors less than 10 nanometers in size, silicon nanowires may be a critical solution to the problem. While they do not conduct electricity in their pure form, the aforementioned process of “doping” boron and phosphorus particles into the wires can resolve this problem. This creates positive and negative particles that can carry the electrons and thus the electrical current.

However, the process is not without its obstacles. Compared to silicon in block form, adding impurities to wires is notoriously difficult. Also, boron particles are known to easily escape to the extremities of the wires if they are oxidized. Hence, there was also the issue of how to exactly control the conductive properties of the doped wires.

In their research, Professor Chang’s team modified simpler, preexisting quantum simulations to fit the more realistic core-shell atomic structure model. Through this process, the team was the first to be able to elucidate how and why exactly boron impurities escape so easily outside the wire cores to the oxidant shells. The simulations also showed that added phosphorus atoms – while they do not escape outside the core - form electronically neutral pairs that impair electrical efficiency and even “blockade” the passage of further current. In comparison to silicon films, the finer cross sections and larger surface areas of silicon nanowires make these issues more prominent.

Professor Chang commented that “this research methodology might justify the establishment of the core-shell nanowires model as the scientific standard” and that it would “facilitate the 3 dimensional study and simulation of electrical devices around 10 nanometers in size.” The study was funded by the Ministry of Education, Science and Technology, and the Korean Research Foundation. The paper was published in the prestigious nanoscience journal Nano Letters.